Filter module for a video decoding system

ABSTRACT

Systems and methods are disclosed for filter modules in a video display system or network. One embodiment relates to a method for operating a filter module in a video display network comprising determining a picture type, display type and operation of the display network. The method further comprises determining, in real time, a filter configuration from a plurality of possible filter configurations based on the determined picture type, display type and operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/386,312filed Mar. 11, 2003 titled “Filter Module for a Video Decoding System”,which is related to, and claims benefit of and priority from,Provisional Application No. 60/420,226 filed Oct. 22, 2002, titled“Filter Module for a Video Decoding System”, the complete subject matterof which is incorporated herein by reference in its entirety.

This application also makes reference to U.S. Provisional ApplicationSer. No. 60/420,152 filed Oct. 22, 2002, titled “A/V Decoder Having AClocking Scheme That Is Independent Of Input Data Streams”; U.S. patentapplication Ser. No. 10/300,371 filed Nov. 20, 2002, titled “A/V DecoderHaving A Clocking Scheme That Is Independent Of Input Data Streams”;U.S. Provisional Application Ser. No. 60/420,136 filed Oct. 22, 2002,titled “NCO Based Clock Recovery System and Method for A/V Decoder”;U.S. patent application Ser. No. 10/313,237 filed Dec. 5, 2002, titled“NCO Based Clock Recovery System and Method for A/V Decoder”; U.S.Provisional Application Ser. No. 60/420,344 filed Oct. 22, 2002, titled“Data Rate Management System and Method for A/V Decoder”; U.S.Provisional Application Ser. No. 60/420,342 filed Oct. 22, 2002, titled“A/V System and Method Supporting a Pull Data Flow Scheme”; U.S. patentapplication Ser. No. 10/300,234 filed Nov. 20, 2002, titled “A/V Systemand Method Supporting a Pull Data Flow Scheme”; U.S. ProvisionalApplication Ser. No. 60/420,140 filed Oct. 22, 2002, titled “HardwareAssisted Format Change Mechanism in a Display Controller”; U.S. patentapplication Ser. No. 10/300,370 filed Nov. 20, 2002 titled “HardwareAssisted Format Change Mechanism in a Display Controller”; U.S.Provisional Application Ser. No. 60/420,151 filed Oct. 22, 2002, titled“Network Environment for Video Processing Modules”; U.S. patentapplication Ser. No. 10/314,525 filed Dec. 9, 2002 titled “NetworkEnvironment for Video Processing Modules”; U.S. Provisional ApplicationSer. No. 60/420,347 dated Oct. 22, 2002, titled “Video Bus For A VideoDecoding System”; and U.S. Provisional Application Ser. No. 60/420,308filed Oct. 22, 2002, titled “Multi-Pass System and Method SupportingMultiple Streams of Video” are each incorporated herein by reference intheir entirety.

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BACKGROUND OF THE INVENTION

The present invention relates to a filter module. More specifically, thepresent invention relates to a filter module for a video decodingsystem, where the video decoder system is adapted to process, decode ordecompress one or more input data streams (alternatively referred to as“input data”, “input data streams” or “data streams”).

It is contemplated that the video decoding system may accommodate one ormore picture types, display types and operations. Such different picturetypes display types and operations may require different filters usedfor scaling, sub-sampling, de-interlacing, etc. The addition of multiplefilter modules as such may cause the video decoder system to be morecomplex, large and consume more energy.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Features of the present invention may be found in a filter module used,in one embodiment in a video decoding system and method of determiningsuch a filter module on the fly (i.e., in real time). More specifically,the filter module is adapted to be used in a network in the videodecoding system, wherein the network is adapted to form at least onedisplay pipeline from a plurality of display pipelines.

One embodiment of the present invention relates to a method of operatinga filter module in a for a video display system. In this embodiment, themethod comprises determining a picture type of the display network,determining a display type of the display network and determining anoperation of the display network. The method further comprisesdetermining, in real time, a filter configuration from a plurality ofpossible filter configurations based on the determined display network,display type and operation of the display network.

Yet another embodiment of the present invention relates to a method ofoperating a filter module in a video display system. This methodcomprises determining if a picture type of the display network is framebased video, field based video or graphics; determining if a displaytype of the display network is progressive or interlaced; anddetermining if an operation of the display network is at least noscaling, interpolation or decimation. The method further comprisesdetermining, in real time, a filter configuration form a plurality ofpossible filter configurations based on the determined picture type,display type and operation.

Still another embodiment of the present invention relates to a filtermodule used in a network for processing data, the filter module beingadapted to form one filter configuration from a plurality of possiblefilter configurations. In this embodiment, the network is adapted toform at least one display pipeline from a plurality of displaypipelines. The filter module may comprise one or more FIR filters, oneor more ARC filters and one or more AFF filters. Additionally, thefilter module may also include such filter functions as pre-filteringand de-interlacing. It is contemplated that each filter module may becomprised of one filter, a plurality of the same type of filter, or acombination of different types of filters or filter functions.

These and other advantages and novel features of the present invention,as well as details of an illustrated embodiment thereof, will be morefully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates one embodiment of a block diagram of an A/V decoderin accordance with the present invention;

FIG. 2 illustrates one embodiment of a block diagram of an A/V systemhaving a network in accordance with the present invention;

FIG. 3 illustrates one embodiment of a filter module having one or morefilters in accordance with the present invention;

FIG. 4 illustrates one embodiment of a block diagram of a networkenvironment for videoprocessing modules;

FIG. 5 illustrates another embodiment of a block diagram of a networkenvironment in accordance with the present invention;

FIG. 6 illustrates one embodiment of a register DMA controller inaccordance with one embodiment of the present invention;

FIG. 7 illustrates embodiments of block diagrams of nodes in accordancewith the present invention;

FIG. 8 illustrates one embodiment of a network module in accordance withone embodiment of the present invention;

FIG. 9 illustrates one embodiment of a high level flow diagram of amethod of determining a filter module in a video decoding system inaccordance with one embodiment of the present invention; and

FIGS. 10A, 10B and 10C illustrate a flow chart illustrating a method ofdetermining a filter module used in a video decoding system inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is made with reference to the appendedfigures.

One embodiment of the present invention relates to filter modules. Morespecifically, one embodiment relates to filter modules in a networkenvironment in an audio/video decoder system. FIGS. 1 and 2 illustrateblock diagrams of embodiments of an A/V decoders in accordance with thepresent invention.

FIG. 1 illustrates one embodiment of a high level block diagram ofembodiment of an A/V decoder, generally designated 110. More detailabout the A/V decoder is provided in U.S. Provisional Application Ser.No. 60/420,152 filed Oct. 22, 2002, titled “A/V Decoder Having AClocking Scheme That Is Independent Of Input Data Streams” and U.S.patent application Ser. No. 10/300,371 filed Nov. 20, 2002, titled “A/VDecoder Having A Clocking Scheme That Is Independent Of Input DataStreams”, the complete subject matter of each of which is incorporatedherein by reference in its entirety. In the illustrated embodiment, thedecoder 110 comprises a system time reference recovery device 112(alternatively referred to as an “STR recovery device”) having one ormore input data streams 118.

The STR recovery device 112 is illustrated communicating with an A/Vdata processing device 114. In one embodiment of the invention, STRrefers to a reference time value. It is anticipated that different ormore complex systems are also possible and within the scope of thepresent invention. For example if the A/V decoder 110 has more than onedata source, the decoder may include more than one STR recovery device,where the number of STR recovery devices may or may not correspond tothe number of data sources. More detail about the STR recovery devicesis provided in U.S. Provisional Application Ser. No. 60/420,136 filedOct. 22, 2002, titled “NCO Based Clock Recovery System and Method forA/V Decoder” and U.S. patent application Ser. No. 10/313,237 filed Dec.5, 2002, titled “NCO Based Clock Recovery System and Method for A/VDecoder”, the complete subject matter of each of which is incorporatedherein by reference in its entirety.

As an alternative to the MPEG scheme, an A/V system incorporating an A/Vdecoder may accept analog television signals as inputs. In thisembodiment, the analog video input goes through, and is processed ordecoded by, the A/V data processing device 114, which may comprise avideo decoder or VDEC. Likewise, analog audio goes through, and isprocessed or decoded by, the A/V data processing device 114 which mayfurther comprise a BTSC audio decoder (alternatively referred to as a“ADEC” or “BTSC”). More detail about the data processing devices isdisclosed in U.S. Provisional Application Ser. No. 60/420,342 filed Oct.22, 2002, titled “A/V System and Method Supporting a Pull Data FlowScheme” and U.S. patent application Ser. No. 10/300,234 filed Nov. 20,2002, titled “A/V System and Method Supporting a Pull Data Flow Scheme”,the complete subject matter of which is incorporated herein byreference.

One embodiment of the present invention uses a system clock (a fixedsystem clock for example) to control the data processing. Morespecifically, the system clock may be used to control the data processin a network in accordance with the present invention. It iscontemplated that the STR recovery device 112 may be locked to theanalog video line rate. The analog hysncs are converted into apsuedo-STR using a simple counter in one embodiment. The STR recoverydevice 112 locks to this psuedo-STR and broadcasts the recovered STR tothe rest of the decoder 110. The broadcast STR is used to control theoutput rates as provided previously.

FIG. 1 further illustrates a rate managed output device 116, which isillustrated as communicating with the data processing device 114. In theillustrated embodiment, the rate managed output device 116 has one ormore A/V outputs 120, which are output at the same or different rates.In FIG. 1, three A/V outputs, generally designated 120, are illustrated.For example, one A/V output is output at 29.999 frames per second(alternatively referred to as “fps”), one is output at 30.001 fps andone is output at 30.000 fps.

In one embodiment, the A/V data processing device 114 includes a networkenvironment for video processing modules. The data processing device 114bases audio and video processing on multiples of a single, fixed clock,a 27 MHz crystal clock for example. It is contemplated that, as a singlefixed clock is used, the processing is not constrained by clockboundaries. Video and audio may be muxed between modules. It is furthercontemplated that such architecture may be made orthogonal, and easy tocontrol.

In accordance with one embodiment, all data, including all audio andvideo data, is processed by a network environment and transferred usinga “pull” model or mode, even though typical A/V streams (e.g., MPEG) areadapted to operate according to a push model or mode. The outputsrequest data as needed. Each module in the A/V decoder 110 may supplydata to its outputs at the rate it is requested. Because a pull model ormode is used, the data processing clock (i.e., the system clock) is nottied to the input data rate. For example, the audio decoder may beclocked at 243 MHz, 133 MHz, or any other reasonable rate. The audiodecoder clock does not need to “track” the input data rate.

Conventional A/V decoders use a VCXO or VCXO-PLL to lock the chip clockto the input data rate. However, one embodiment of the present inventionuses rate managed output devices 116 and the associated SRC devices tochange or adjust the video and audio output rates.

It is contemplated that, in one embodiment of the present invention, theoutput data rate tracks the STR. If the A/V decoder decodes multiplevideo streams, there may be multiple STRs. Each output data rate tracksan associated STR. The process of controlling the output rates may becalled “rate management.” In one embodiment, the rate managed outputdevice 116 (alternatively referred to as a “output rate manager” or“output rate manager PLL”), comprising for example a digital PLL, isused to compare the output rate with the STR, and adjust the output rateaccordingly, such that the output data rate matches the STR and theinput data rate. In one embodiment the A/V decoder may include severaloutput rate managers, one for each output of the A/V decoder. Moredetail about rate managers is provided in U.S. Provisional ApplicationSer. No. 60/420,344 filed Oct. 22, 2002, titled “Data Rate ManagementSystem and Method for A/V Decoder” the complete subject matter of whichis incorporated herein by reference.

FIG. 2 illustrates one embodiment of a block diagram of a video decodingsystem or network in accordance with the present invention. In thisembodiment, the network 216 is adapted to receive video-in 208 (from amemory for example) and output video-out 220.

FIG. 2 further illustrates the system or network 216 containing at leastone display pipeline 240 and filter module 250. In one embodiment of thepresent invention, the display pipeline 240 is changeably formed bychaining, coupling or concatenating one or more network nodes togetheron the fly (i.e., in real time), depending on the network requirements.It is contemplated that the nodes may be re-configured, so that aplurality of display pipelines 240 may be formed, each pipeline having adifferent functionality depending on the nodes that are concatenatedtogether. Moreover, in one embodiment, it is contemplated that thenetwork 240 may change the display pipeline 240 every 1/60^(th) of asecond for example (i.e., real time).

In the illustrated embodiment, filter module 250 comprises one or morefilters adapted to be configured (i.e., coupled together in the filtermodule) on the fly (i.e., in real time) depending on the picture type(i.e., frame based video, field based video and graphics), display type(i.e., progressive or interlace) and the operation (i.e., no scaling,ARC, interpolation and decimation). It is contemplated that the filtermodule may comprise an FIR filter, ARC, AFF, prefiltering andde-interlacing, alone or in some combination.

In this embodiment, a register DMA controller 242 (alternativelyreferred to as an “RDC”) is illustrated coupled to the network 216 andone or more register update lists 246 (alternatively referred to as an“RUL”). The RDC 242 is adapted to support multiple, configurablepipelines 240 and the configurable filter module 250 by accessing andfetching (i.e., obtaining) one or more instructions from the RUL 246 andproviding such instructions to configure at least one display pipeline240 from a plurality of possible display pipelines and the requiredfilters in the filter module 250. In one embodiment, the RDC 242accesses the RUL 246 (fetching the instructions) in response to the oneor more trigger signals 244 (real time DMA trigger signals or eventsgenerated by the last node in the pipeline 240 for example). It iscontemplated that, if the network 216 did not have an RDC 242 associatedtherewith, the network 216 would have to reconfigure the pipeline oneregister at a time.

FIG. 3 illustrates one embodiment of a filter module 350 similar to thefilter module 250 of FIG. 2. In this embodiment, the filter comprisesone or more filters (F1 through Fn designated 352 through 358respectively). In this embodiment, the filters are adapted to beconfigured (i.e., coupled together) on the fly by the RDC and RULdepending on the picture type (i.e., frame based video, field basedvideo and graphics), display type (i.e., progressive or interlace) andthe operation (i.e., no scaling, ARC, interpolation and decimation) asillustrated in Table 1. For example, it is contemplated that F1 maycomprise a FIR, F2 may comprise an AFF and F3 may comprise an ARC.

FIG. 4 illustrates one embodiment of a block diagram of a networkenvironment (alternatively referred to as a “display engine”) for videoprocessing modules in accordance with the present invention. Thenetwork, generally designated 400, is adapted to support a pull datascheme and comprises at least a register DMA controller, one or morenodes, one or more links, and one or more network modules. In thisembodiment, the register DMA controller 410 (also referred to as a“bridge”) is responsible for register access within the system 400. Theregister DMA controller 410 connects the register bus 412 (alternativelyreferred to as “RBUS”) with the video register bus 414 (alternativelyreferred to as “VBUS”). However, other decoders, with or without STRrecovery devices, are contemplated. More detail about the network isprovided in U.S. Provisional Application Ser. No. 60/420,151 filed Oct.22, 2002, titled “Network Environment for Video Processing Modules” andU.S. patent application Ser. No. 10/314,525 filed Dec. 9, 2002 titled“Network Environment for Video Processing Modules”, the complete subjectmatter of which is incorporated herein by reference.

The system 400, in one embodiment, further comprises one or more nodes416 (two nodes 416A & 416B are illustrated where node 416B comprise aconfigurable filter module). Nodes 416 are modules that process videoinformation (nodes 416A & 416B are illustrated having video-in signals414 and video-out signals 426 respectively). Some examples of nodescomprise video scalers, 2D graphics compositors, video encoders, etc.

FIG. 4 further illustrates one or more links 418 (links 418A & 418B areillustrated). In this embodiment, the links 418 comprise a set ofsignals or buses that tie or connect at least two nodes together (link418A is illustrated coupling node 416A to network module 420 while link418B is illustrated coupling network module 420 to node 416B). The links418 are adapted to transfer information using a predefined protocol.However, other decoders, with or without STR recovery devices, arecontemplated. More detail about the link is provided in U.S. ProvisionalApplication Ser. No. 60/420,347 dated Oct. 22, 2002, titled “Video BusFor A Video Decoding System” the complete subject matter of which isincorporated herein by reference.

Additionally, system 400 comprises one or more network modules 420 that,in this embodiment, are specialized nodes that don't perform videoprocessing functions. Rather, the network module 420 connects at leasttwo or more links 418 together, routing information between them. Ingeneral, the system 400 may include a number of pipelines (i.e., displaypipelines) formed by chaining multiple nodes together. Each displaypipeline starts at one or more nodes 416, where it is contemplated thateach node has a memory interface to a frame buffer (not shown in FIG.4). Functions are added to the pipeline by cascading more nodes to thepipelines. Finally, a pipeline ends at one or more nodes, where eachsuch node is a desired output channel.

In accordance with the present invention, the register bus or RBUS 412is connected to the video register bus or VBUS 414 through the registerDMA controller 410. In this embodiment, both buses use identicalsignaling and protocols. The register DMA controller 410 acts as a slaveto the RBUS 412 and forwards transactions to VBUS 414. In addition,register DMA controller 410 may perform one or more Register DMAoperations, which comprises decoupling a host from video timing byautomating mode changes.

In one embodiment, register DMA controller 410 includes four interfaces.There are two register bus interfaces, one interface 428 coupling theregister DMA controller 410 to RBUS 412 and the other interface 430coupling the register DMA controller 410 to VBUS 414. The thirdinterface is a memory bus interface 432 coupling the register DMAcontroller 410 to the memory bus 422 (alternatively referred to as“MBUS”). The memory bus 422 is used to access register writes from anexternal memory. Finally the last interface 434 comprises an array ofsignals coming from at least one of the nodes 416, which are used as DMAtriggers.

In accordance with one embodiment, display modes or pipelines areconfigured or changed using control registers. Instead of updating thedisplay modes one at a time, the host uses the register DMA controller,feature or operation to automate the process. In this embodiment, theRegister DMA comprises three entities: a register update list, a DMAdescriptor and a DMA trigger as provided below.

FIG. 5 illustrates another embodiment of a block diagram of a network ordisplay engine according to the present invention. In this embodiment,the network, generally designated 500, video processes modules and isfurther adapted to support a pull data scheme. Register DMA controller510 is responsible for register accesses within the network 500. Theregister DMA controller 510 connects the register bus or RBUS 512 withthe video register bus or VBUS 514.

In this embodiment, the RBUS 512 comprises at least one video-in module524 coupled to and communicating with at least one node (Node 516A forexample). Further the RBUS 512 may comprise a memory interface 536coupled to and communicating with at least the memory bus 522 (usingmemory bus interface 532 for example) and main memory 538; and a hostinterface 540 communicating with at least the memory bus 522 (usingmemory bus interface 532 for example), host 542 and register DMAcontroller (using interface 528 for example).

The network 500, in this embodiment, comprises a plurality of nodes 516(nine nodes 516A-516I are illustrated) adapted to process videoinformation. While only nine nodes are illustrated, more (or less) nodesare contemplated. Again, the nodes 516 process video information (node516A is illustrated having video-in signals 524 communicating therewith,node 516D comprises a filter module, while nodes 516H and 516I areillustrated having video-out signals 526A and 526B respectivelycommunicating therewith). In this embodiment an optional MPEG decoder517 is illustrated coupled to node 516C, and communicating with videobus 514, register DMA controller 510 and memory bus 522.

FIG. 5 further illustrates a plurality of links 518 (12 links 518A-518Lare illustrated). Again, while 12 links 518 are shown, a differentnumber is contemplated. In this embodiment, the links 518 comprise a setof signals or buses that tie at least two nodes 516 together andtransfer information using a predefined protocol.

Additionally, network 500 comprises a plurality of specialized nodes ornetwork modules 520 that, in this embodiment, connect at least two ormore links 518 together, routing information therebetween. It is againcontemplated that, in general, the network 500 may include a number ofdisplay pipelines formed by chaining multiple nodes together using thenetwork modules 520 to switch between the nodes 516, thus varying orchanging the pipeline. Each pipeline starts and ends at one or morenodes 516, where it is contemplated that each node has a memoryinterface 536 to a frame buffer. Functions are added to the pipelines bycascading that pipeline with more nodes.

In accordance with the present invention, the RBUS 512 is connected tothe VBUS 514 through the register DMA controller 510. In thisembodiment, both buses use identical signaling and protocols. Theregister DMA controller 510 acts as a slave to the RBUS 512 and forwardsall the transactions to VBUS 514. In addition, the Register DMA 510decoupes the host from video timing using automating mode changes to

FIG. 6 illustrates one embodiment of a block diagram of a register DMAcontroller 610 including four interfaces similar to that providedpreviously. There are two register bus interfaces, one interface 628coupling the register DMA controller 610 to RBUS 612 and the otherinterface 630 coupling the register DMA controller 610 to VBUS 614. Thethird interface is a memory bus interface 632 coupling the register DMAcontroller 610 to the memory bus 622. Finally, interface 634 comprisesan array of signals (0-n) coupled to at least one of the nodes 616,which are used as DMA triggers, and generally designated 635.

The register DMA controller is adapted to support register DMAoperations or functions in accordance with the present invention. Fourinterfaces are coupled to and communicating with the register DMAcontroller as provided previously: one interface coupling the registerDMA controller to RBUS; one interface coupling the register DMAcontroller to VBUS; one interface coupling the register DMA controllerto the memory bus; and one interface, comprising an array of signals,which are used as DMA triggers. It is further contemplated that, in thisembodiment, the register DMA controller is comprised of at least fivemodules including a DMA engine; descriptors; RUL FIFO; one or more BUSmultiplexers; and one or more filters.

In this embodiment, the DMA engine accesses one or more RULs from themain memory using the memory bus used to configure the filter module onthe fly (i.e., in real time). The engine services the DMA channelsaccording to the configuration specified by the descriptors. Further,each DMA channel consists of a trigger and a descriptor, such that, inthis embodiment the number of DMA channels equals the number of triggersand descriptors.

Register DMA controller further comprises an RUL FIFO coupled to atleast the DMA engine, which is adapted to buffer the bursty memory businto the slower register bus. In this embodiment, the size of the FIFOis optimized to reduce the DMA response time. The register DMAcontroller further includes at least one filter that, in one embodiment,lowers the DMA response time by reducing the traffic on the videoregister bus. The filter is adapted to screen the register bus,forwarding accesses related to the video register bus. A bus multiplexeror mux is illustrated coupled to the RUL FIFO and filter, and is adaptedto convert RULs into individual register writes. In addition, the BUSmux arbitrates the video register bus between the DMA register writesand register accesses filtered from the register bus.

FIG. 7 illustrates different embodiments of the nodes, generallydesignated 716, used in one embodiment of the network. The network, inaccordance with the present invention, is adapted to perform videoprocessing functions similar to a display engine, including videoplayback, scaling, encoding, etc. It is contemplated that each node 716in the network may be generally divided into three categories accordingto its position in a display pipeline: entry, exit, and intermediate.Video data enters a display pipeline at an “entry node” designated 716Aand leaves at an “exit node” designated 716B. All the nodes in-betweenare referred to as “intermediate nodes” or “nodes” designated 716C.Examples of entry nodes 716A include MPEG display feeders, playbackengines, etc. Examples of exit nodes 716B include video encoders,capture engines, etc. Examples of intermediate nodes 716C includescalers, compositors, etc. It is further contemplated that the positionof each node in the pipeline configuration is not fixed; rather itsposition varies depending on the display pipeline (i.e., an entry nodein one pipeline may be an intermediate node in another displaypipeline).

As illustrated, the nodes 716 each generally include at least one inputand output interface or link 718 communicating therewith. It iscontemplated however that each node 716 is adapted to have multipleinput or output links 718A & 718B coupled thereto and communicatingtherewith (a compositor for example has multiple input links).Furthermore, each node 716 may also have an optional RBUS 714, MBUS 722or some other optional auxiliary interface 780 (a DMA trigger for theregister DMA controller for example) communicating therewith. If thenode 716 is an entry node 716A, it is contemplated that the input linkis an MBUS interface 722 as illustrated. For exit nodes 716B, the outputis replaced by a dedicated output 750 (e.g., a memory interface for acapture engine or an analog video output for a video encoder).

As provided previously, a display pipeline in the network starts orbegins at one or more entry nodes 716A. The entry node 716A isresponsible for feeding video to the downstream nodes 716 and includes,for example, MPEG display feeders and playback engines. In oneembodiment, the input to an entry node 716A may comprise RBUS and memoryinterfaces. Its output may comprise one or more output links 718B. Inaddition, the entry node 716A may include one or more auxiliaryinterfaces 770 such as a DMA trigger for the register DMA controller.

The intermediate node 716C, in one embodiment, may have specificfunctions comprising scaling, compositing, etc. One or more nodes areadded to a display pipeline as its features are used to satisfy certainoutput requirements. In general, the input and output of an intermediatenode 716C comprises one or more links 718A & 718B as providedpreviously. In addition, the intermediate node 716C may have an optionalregister bus interface or some other auxiliary interface 770 coupledthereto and communicating therewith.

As provided previously, the display pipeline ends at exit node 716B,which may comprise a video interface such as a composite signal encoderor capture engine for example. In general, the inputs to an exit node716B consist of an input link 718, an optional register bus 712, and avideo output or a memory bus interface 770.

In addition to the functions described previously, the exit nodes 716Bmay include some debugging functions. For example, a checkpoint registermay be written into control packets and read by the register bus 712.This register is programmed in every field to a field dependent number.At the same time, a host may check the progress of the video packets bymonitoring this register through the register bus 712.

It is contemplated that exemplary embodiments of the nodes 712 shouldmeet certain requirements in order to maintain intra- and inter-packetsynchronization. For example, the nodes should be adapted to forwardincoming control packets without being modified. If the node is amulti-input node, one particular input may be designated as the primarylink, such that the control packets of the primary links are forwarded,while control packets from other inputs are terminated.

It is contemplated that exemplary nodes 716 process and output packetsin their arriving order. If the node is a multi-input node, it may onlyoperate on packets corresponding to the same field in time. For example,if the node 716 is a graphics compositor, the i-th field of one inputmay be combined with the i-th field of another input. If the activeinput is not receiving any data, other inputs and the outputs may bestalled.

If the exemplary node 716 is a multi-output node, control and videopackets may be forwarded to all the output links. Stalling by one of theoutput links stalls the inputs as well as the other outputs. Unusedinput or output links of such exemplary nodes 716 may be disabled usingRBUS 712 and the control register. The disabled link may be excludedfrom controlling other inputs or outputs. For a pipelined node, the nextfield's control packet should not have any effect on current field'svideo packet.

FIG. 8 illustrates one embodiment of a network module 820 in accordancewith the present invention. In this embodiment, the network module 820comprises a plurality of network interfaces or links generallydesignated 818 and switches, described in greater detail below. One ormore network modules are used to connect one or more nodes, forming atleast one display pipeline from a plurality of possible displaypipelines. Since the nodes may be re-configured, it is contemplated thatdisplay pipelines having different functionality may be implemented fordifferent applications. In other words, the display pipelines aredynamic and not static.

The network interfaces 818, in this embodiment, comprise input andoutput links 818A & 818B respectively, and an optional register bus 812.In this embodiment, m input links 818A and n output links 818B areillustrated, where m and n may be the same or different. It iscontemplated that m may be greater than, equal to or less than n (i.e.,the number of input links 818A may be greater than, equal to or lessthan the number of output links 818B).

It is contemplated that different types of network modules may be usedwithin the register DMA controller or display engine. The network module820, in accordance with the present invention, is comprised of an arrayof switches coupled together using predefined topology. This topologydetermines the network module's routing capabilities, as well as theimplementation cost.

As discussed, in one embodiment of the present invention a networkdisplay engine may include a filter node or module, wherein such filtermodule may be used for scaling, sub-sampling, de-interlacing, etc. inthe network. In one embodiment of the present invention, the filtermodule is comprised of one or more filters including for example, one ormore FIR filters, one or more ARC filters and one or more AFF filters.Additionally, the filter module may also include such filter functionsas pre-filtering and de-interlacing. It is contemplated that each filtermodule may be comprised of one filter, a plurality of the same type offilter, or a combination of different types of filters or filterfunctions illustrated in Table 1 for example.

It is also contemplated that the filter module comprising one or morefilters is dependant on the picture type (i.e., frame based video, fieldbased video and graphics), display type (i.e., progressive or interlace)and the operation (i.e., no scaling, ARC, interpolation and decimation)as illustrated in Table 1. In this embodiment, the configuration of thefilters in the filter module may change on the fly as controlled by theDMA and the RUL (i.e., one or more register write instructions).

As illustrated, an FIR filter (a 2D polyphase FIR filter for example)may be used to perform interpolation and decimation in picture anddisplay type. A single set of coefficients may be used for differentinterpolation ratios. It is contemplated that the coefficients may varyaccording to the decimation ratio. Pre-filtering (memory-to-memorydecimation for example) may be used if the scale factor is smaller thana predetermined amount. Pre-filtering is utilized to alleviate the peakbandwidth requirement of an FIR filter for example. In one embodiment,pre-filtering may be used in the decimation operation in any picture anddisplay type.

An adaptive-temporal filtering method is preferred for de-interlacing afield-based video. However, it is also contemplated that verticalinterpolation with phase adjustment may be used for de-interlacing afield based video. An ARC filter (a 1D polyphase filter for example) maybe used to change the aspect ratio of a graphics plane using horizontalscaling. However, 1D polyphase filters may have a different frequencyresponse than its video counterpart as graphics are synthetic andcontain more high frequency features. An AFF is a vertical low passfilter used to filter a frame-based picture before the picture may bedisplayed on an interlace device. It is contemplated that a video AFFmay have a different frequency response than a graphics AFF. However,some SD frame pictures are pre-filtered for displaying an interface. Inthat case, no AFF is required.

TABLE 1 Picture Display Type Type Operation FIR Pre-filteringDe-interlace ARC AFF Description Frame based Progressive No scaling Nofiltering is used. video Interpolation * High quality filtering is used.Decimation * * Interlace No scaling * The FIR filter could subsume theInterpolation * * function of the AFF filter. Decimation * * * Fieldbased Progressive No scaling * The FIR filter could subsume the de-video Interpolation * * interface function. Decimation * * * InterlaceNo scaling No filtering is used. Interpolation * High quality filteringis used. Decimation * * Graphics Progressive No scaling No filtering isused ARC * The FIR filter could subsume the Interpolation * function ofthe ARC. Decimation * * Decimating a graphics plane is seldom used. Thisfeature is optional. Interlace No scaling * Anti-flutter filtering isapplied on top ARC * * of other filter operations. Interpolation * *Decimation * * *

As illustrated in Table 1, no filtering is used in a first configurationof a filter module comprising frame based video with a progressivedisplay type during a no scaling operation. Therefore, no filters areused in this first filter module. High quality filtering is used in asecond configuration of frame module comprising frame based video with aprogressive display type during an interpolation operation. An FIRfilter may be used in this display mode. Table 1 also illustrates thathigh quality filtering is also used in a third configuration of a framemodule comprising frame based video with a progressive display typeduring a decimation operation. An FIR filter and pre-filtering may beused in this display mode.

A fourth configuration of the filter module illustrated in Table 1 isused with frame based video, with an interlaced display type during a noscaling operation. The module comprises an AFF filter, where the FIRfilter may subsume the functions of the AFF filter. However, some framepictures are pre-filtered for displaying as an interface. In thisconfiguration, no AFF filter is used. A fifth configuration of a framemodule used in frame based video with an interlaced display type duringan interpolation operation is also illustrated. This module comprises aFIR filter used with an AFF filter. A sixth configuration of a filtermodule used in frame based video with an interlaced display type duringa decimation operation comprises a combination of FIR filter andpre-filtering.

Table 1 illustrates a seventh configuration of a filter module used withfield based video with a progressive display type during a no scalingoperation, comprising a de-interlace filter, where the FIR filter maysubsume the function of the de-interlace filter. An eighth configurationof a frame module used with field based video with a progressive displaytype during an interpolation operation is illustrated. In this module, aFIR filter may be used with a de-interface filter, where again the FIRfilter may subsume the de-interlace function. A ninth configuration of afilter module comprising an FIR filter, pre-filtering and de-interlacingmay be used in field based video with a progressive display type duringa decimation operation.

No filtering is needed in a tenth configuration of a filter moduleillustrated in Table 1, used with field based video with an interlaceddisplay type during a no scaling operation. An eleventh configuration ofa filter module used in field based video with an interlaced displaytype during an interpolation operation is further illustrated. In thismodule, high quality filtering is provided by an FIR filter. A twelfthconfiguration of a filter module comprising an FIR filter andpre-filtering may be used in a field based video with an interlaceddisplay type during a decimation operation.

Table 1 illustrates a thirteenth configuration of a filter module thatuses no filtering with a graphics picture type with a progressivedisplay type during a no scaling operation. A fourteenth configurationof a filter module comprises an ARC filter, where an FIR filter maysubsume the function of the ARC filter in graphics picture type withprogressive display type during an ARC operation. A fifteenthconfiguration of a frame module used with a graphics picture type with aprogressive display type during an interpolation operation is alsoillustrated. In this configuration, an FIR filter may be used, whereagain the FIR filter may subsume the functions of an ARC filter. Asixteenth configuration of a filter module, comprising an FIR filter andpre-filtering, may be used in a graphics picture type having aprogressive display type during a decimation operation.

A seventeenth configuration of a filter module is illustrated in Table 1and comprises an AFF or anti-flutter filter used with a graphics picturetype with an interlaced display type during a no scaling operation. Aneighteenth configuration of a filter module, comprising ARC and AFFfilters, where the anti-fluttering filtering is applied on top of otheroperations, is used with a graphics picture type having interlaceddisplay type during an ARC operation. A nineteenth configuration of aframe module used with a graphics picture type with an interlaceddisplay type during an interpolation operation is illustrated, where thefilter module comprises FIR and AFF filters. A twentieth configurationof a filter module, comprising an FIR filter, pre-filtering and an AFFfilter, may be used with a graphics picture type having interlaceddisplay type during a decimation operation. While a frame module havingtwenty configurations is provided, more and different configurations arecontemplated.

FIG. 9 illustrates a high level flow diagram of a method for determiningthe configuration of filters from a plurality of filters in a filtermodule, generally designated 900. More specifically, the flow diagramillustrates a method for determining the configuration of a filtermodule in a video decoding system. In this embodiment, the method 900comprises determining a picture type (for example frame based video,field based video or graphics) as illustrated by block 910. Method 900comprises determining the display type (for example progressive orinterlaced) and the operation (for example no scaling, interpolation,decimation or ARC) as illustrated by blocks 912 and 914. The filtermodule is then determined on the fly (i.e., using FIR filters,pre-filtering, de-interlace filtering, ARC filters, AFF filters or somecombination) as illustrated by block 916.

FIGS. 10A, 10B and 10C illustrate one embodiment of method fordetermining a filter configuration (i.e., determining one configurationfrom a plurality of possible configurations) in a filter mode, generallydesignated 1000. More specifically, the flow diagram illustrates amethod for determining a filter module in a network video decodingsystem adapted to form a display pipeline from a plurality of possibledisplay pipelines. This method comprises determining if the picture typeis a frame based video, field based video or graphics as illustrated bydiamonds 1010, 1012 and 1014 respectively.

Method 1000, in one embodiment, comprises determining if the displaytype is progressive or interlaced as illustrated by diamonds 1016 and1018 respectively. The method determines if the operation is no scaling,interpolation, decimation or ARC as illustrated by diamonds 1020, 1022,1024 and 1026 respectively. The method then comprises determining thefilter module (comprising one or more FIR filters, pre-filtering,de-interlace filtering, one or more ARC filters, AFF filters or somecombination) on the fly as illustrated by block 1028.

Many modifications and variations of the present invention are possiblein light of the above teachings. Thus, it is to be understood that,within the scope of the appended claims, the invention may be practicedotherwise than as described hereinabove.

1. A video display system, said system comprising: a plurality offilters for filtering a corresponding plurality of video streams; and aregister direct memory access controller for simultaneously configuringthe plurality of filters, wherein each of the corresponding plurality offilters are configured for a particular one of the plurality of videostreams, wherein each of the plurality of filters are configured basedat least in part on a determination of the picture type of theparticular one of the plurality of video streams and the display type ofthe at least one display device; and at least one output forsimultaneously outputting each of the plurality of video streamsfiltered by the plurality of filters.
 2. The system of claim 1, whereinthe determination of the picture type of the plurality of video streamsfurther comprises determining if the picture type is frame based video,field based video, or graphics.
 3. The system of claim 1, wherein thedetermination of a display type of the at least one display devicecomprises determining if said at least one display type is progressiveor interlaced.
 4. The system of claim 1, further comprising: aninterpolator operable to interpolate selected ones of the plurality ofvideo streams; a decimator operable to decimate other selected ones ofthe plurality of video streams; and wherein the register direct memoryaccess controller configures each of the plurality of filters based atleast in part on whether the interpolation or decimation operations isto be performed on the particular one of the plurality of video streams.5. The system of claim 1, wherein the register direct memory accesscontroller configures the plurality of filters in accordance with atleast one register write instruction.
 6. The system of claim 1, whereinthe at least one display further comprises a plurality of simultaneousdisplays, wherein each of the plurality of simultaneous displays areassociated with a particular one of the video streams, and wherein theregister direct memory access controller configures the filter based atleast in part on the display type of the one of the plurality ofsimultaneous displays that is associated with the particular videostream.
 7. An apparatus for providing displayable video, said apparatuscomprising: a plurality of filters operable to filter a correspondingplurality of video streams; and a register direct memory accesscontroller operably connected to the plurality of filters tosimultaneously configure the plurality of filters, wherein each of thecorresponding plurality of filters are configured for a particular oneof the plurality of video streams, wherein each of the plurality offilters are configured based at least in part on a determination of thepicture type of the particular one of the plurality of video streams andthe display type of the at least one display device; and at least oneoutput operable to simultaneously output each of the plurality of videostreams filtered by the plurality of filters.
 8. The apparatus of claim7, wherein the determination of the picture type of the plurality ofvideo streams further comprises determining if the picture type is framebased video, field based video, or graphics.
 9. The apparatus of claim7, wherein the determination of a display type of the at least onedisplay device comprises determining if said at least one display typeis progressive or interlaced.
 10. The apparatus of claim 7, furthercomprising: an interpolator operable to interpolate selected ones of theplurality of video streams; a decimator operable to decimate otherselected ones of the plurality of video streams; and wherein theregister direct memory access controller is operably connected to theinterpolator and the decimator and configures each of the plurality offilters based at least in part on whether the interpolation ordecimation operations is to be performed on the particular one of theplurality of video streams.
 11. The apparatus of claim 7, wherein theregister direct memory access controller configures the plurality offilters in accordance with at least one register write instruction. 12.The apparatus of claim 7, wherein the at least one display furthercomprises a plurality of simultaneous displays, wherein each of theplurality of simultaneous displays are associated with a particular oneof the video streams, and wherein the register direct memory accesscontroller configures the filter based at least in part on the displaytype of the one of the plurality of simultaneous displays that isassociated with the particular video stream.